1. Field of Invention
The present invention relates to a method and a system for testing a memory. More particularly, the present invention relates to a method and a system for testing a memory using a hash algorithm.
2. Description of Related Art
Semiconductor memory test systems traditionally employ an off-chip test methodology that relies on external test apparatuses—such as Automated Test Equipment (ATE)—for driving the test patterns and performing verification; FIG. 1A is an example of such a system. A memory device (101) receives test pattern vectors (103) from an external Automatic Test Pattern Generation (ATPG 100) hardware; then the output data (104) with previously written test vectors are read back by external hardware for verification (102) of the memory device. Both the ATPG (100) and the verification function (102) may be implemented in an ATE. Though this methodology has been a de-facto standard of memory testing, the cost remained high for the test equipment and the test time. A robust on-chip Built-In Self-Test (BIST) system can significantly reduce the test time and the cost and complexity of external test system.